This invention relates to a method of forming an insulating film on a layer of a polycrystalline substance, and move particularly to a method of forming an insulating film of high breakdown voltage on said layer.
An insulating film formed on a polycrystalline substance layer is demanded to be substantially free from defects, such as pin holes and display a high insulating power with respect to a semiconductor device including multilayered polycrystalline silicon electrodes such as a charge--coupled device (abbreviated as "CCD") of FIG. 1A in which two party overlapping charge--transfer electrodes consist of a group of 4a, 4b, 4c and another group of 5a, 5b, 5c and are all made of polycrystalline silicon or an avalanche injection MOS memory comprising a double layer conducter consisting of a floating gate 8 and control 10 as shown in FIG. 1B. There will now be further detailed the semiconductor devices of FIGS. 1A and 1B. As shown in FIG. 1A, first gate oxide layers 2a, 2b and 2c and second gate oxide layers 3a and 3b are provided on a substrate 1 of P-type single crystal silicon. First polycrystalline silicon electrodes 4a, 4b and 4c each doped with impurity are formed on the first gate oxide layers 2a, 2b and 2c. Second polycrystalline silicon layers 5a and 5b each doped with impurity are mounted on the second gate oxide layers 3a and 3b. The first polycrystalline silicon electrodes 4a, 4b and 4c and the second polycrystalline silicon electrodes 5a and 5b are electrically insulated by an oxide layer 6a, 6b and 6c inserted therebetween.
As shown in FIG. 1B, a first gate oxide layer 7 is formed on a P-type single crystal silicon substrate 1, with a first polycrystalline silicon electrode 8 of a floating gate further formed on the first gate oxide layer 7. A second polycrystalline silicon electrode 10 is formed on the first polycrystalline silicon electrode 8 with an oxide layer 9 inserted therebetween for electrical insulation. The second polycrystalline silicon electrode 10 serves as a control gate. These first and second polycrystalline silicon electrode are both doped with impurity. Diffusion layers 11a and 11b are formed in the surface of the substrate 1, being disposed on both lower sides of the first polycrystalline silicon electrode 8.
The customary method of manufacturing the above-mentioned type of semiconductor device comprises the steps of first forming a first polycrystalline silicon layer, for example, by the chemical vapor deposition (abbreviated as "CVD") process; diffusing phosphor in the polycrystalline silicon layer at a temperature of, for example, 1,000.degree. C. to render said polycrystalline silicon layer conducting; oxidizing the surface of the polycrystalline silicon layer; and using the resultant oxide film as an insulating film between the first polycrystalline silicon layer and a second polycrystalline silicon layer being later formed.
There will now be further described by reference to FIGS. 2A to 2E the prior art method of manufacturing the CCD of FIG. 1A. Referring to FIG. 2A, a first gate oxide layer 14 is formed, for example, on a P-type silicon semiconductor substrate 13. A polycrystalline silicon layer 15 is mounted on the first gate oxide layer 14, for example, by the CVD procss. Phosphor is diffused in the polycrystalline silicon layer 15 at a temperature of, for example, 1,000.degree. C. to render said layer 15 more conducting. Photoresist layers 16a, 16b, 16c are formed photolithographically on the polycrystalline silicon layer 15 now containing phosphor. The exposed portions of the polycrystalline silicon layer 15 are etching method with the photoresist layers 16a, 16b, 16c used as etching masks to provide first layer polycrystalline silicon electrodes 17a, 17b, 17c (FIG. 2B). After removal of the photoresist layers 16a, 16b, 16c, the first gate oxide layers 18a, 18b, 18c are etched off, as shown in FIG. 2C, for example, by an etchant of ammonium fluoride with the first layer polycrystalline silicon electrodes 17a, 17b, 17c used as etching masks. The exposed surface of the P-type silicon semiconductor substrate 13 is heat-treated at a temperature of, for example, 1,000.degree. C. in an oxidizing atmosphere to provide second gate oxide layers 19a, 19b, 19c, (FIG. 2D). At this time, oxide layers 20a, 20b, 20c are also formed on the first layer polycrystalline silicon electrodes 17a, 17b, 17c. Second layer polycrystalline silicon electrodes 21a, 21b, 21c are mounted on the oxide layers 19a, 19b, 19c, 20a, 20b, 20c by the same process as that by which the first layer polycrystalline silicon electrodes 17a, 17b, 17c are formed (FIG. 2E).
According to the above-mentioned prior art process of manufacturing the CCD, insulation between a group of the first layer polycrystalline silicon electrodes 17a, 17b, 17c and another group of the second layer polycrystalline electrodes 21a, 21b, 21c is effected by the intervening oxide layers 20a, 20b, 20c. However, these insulating oxide layers 20a, 20b, 20c have so low breakdown voltage as to chiefly give rise to short-circuit between the first and second layer polycrystalline silicon electrodes. Following are the possible causes which lead to the above-mentioned low breakdown voltage of the insulating oxide layers 20a, 20b, 20c where the photoresist layers 16a, 16b, 16c are lithographically formed under an unsatisfactory condition before providing the polycrystalline silicon electrode 17a, 17b, 17c (FIG. 2B), then the pattern edges of the electrodes project or the subsequent etching of the polycrystalline silicon 15 often roughens the exposed surfaces or edges of the electrodes 17a, 17b, 17c. An electric field tends to be concentrated at the projecting pattern edges or the roughened exposed surfaces and edges of the electrodes 17a, 17b, 17c. Consequently, the insulating oxide layers 20a, 20b, 20c are suppose to decrease in breakdown voltage. Further where, white turbidity appears in part or the whole of the polycrystalline silicon electrodes 17a, 17b, 17c then the breakdown voltage of the insulating oxide layers 20a, 20b, 20c often noticeably falls. The reason is assumed to be that the while turbid portions of the polycrystalline silicon electrodes 17a, 17b, 17c are formed of larger crystal particles than those which do not indicate such aspect; the surfaces of the electrodes often protrude; and consequently an electric field is concentrated at the white furbid portions of the electrodes. For illustration, FIG. 3A shows the 5,000 times magnified electronic microscope replica photograph of the white turbid region of the surface of a polycrystalline silicon electrode having a thickness of 5,000 A. Therefore, formation of an insulating oxide film by the prior art process on the polycrystalline silicon electrodes 17a, 17b, 17c having the above-mentioned defects little elevates the breakdown voltage of said insulating oxide film. Where the first gate oxide layers 18a, 18b, 18c are etched with the first layer polycrystalline silicon electrodes 17a, 17b, 17c used as etching masks, those portions of said oxide layers which lie right below the edges of the electrodes are obliquely hollowed out by etching, causing the edges of the electrodes to take an overhanging form. Where, therefore, the second gate oxide layers 19a, 19b, 19c of FIG. 2D are formed, those portions of said oxide layers which lie near the edges of the polycrystalline silicon electrodes 17a, 17b, 17c are sharply scooped out. While being formed, the second layer polycrystalline silicon electrodes 21a, 21b, 21c are partly carried into said scooped regions, thereby often resulting in insufficient insulation between both groups of polycrystalline silicon electrodes 17a, 17b, 17c and 21a, 21b, 21c. Since, as previously described, the edges of the first layer polycrystalline silicon electrodes 17a, 17b, 17c take an overhanging form, a decline undesirably occurs in beakdown voltage between said electrodes and the silicon substrate 13.
To avoid the above-mentioned disadvantages, it may be considered to provide thick insulating oxide layers 20a, 20b, 20c. As seen from the previously described process of manufacturing the CCD, the formation of the thick insulating oxide layers 20a, 20b, 20c gives rise to an unbalance between the thickness of the oxide layers underlying the first layer polycrystalline silicon electrodes 17a, 17b, 17c and that of the oxide layers underlying the second layer polycrystalline silicon electrodes 21a, 21b, 21c, presenting difficulties in operating the CCD. Further, the first layer polycrystalline silicon layer 15, if made thin, will be wholly oxidized during the formation of an insulating oxide film, giving rise to the drawbacks that short-circuiting will take place between said first polycrystalline silicon layer 15 and the silicon semiconductor substrate 13, and consequently said polycrystalline silicon layer 15 will conversely have to be made unduly thick.